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High stability oscillator SKYWORKS 511NCB-AAAG with DSPLL technology and configurable voltage supply

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High stability oscillator SKYWORKS 511NCB-AAAG with DSPLL technology and configurable voltage supply

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Frequency Stability : ±20ppm

Output Type : -

Voltage - Supply : 3.3V

Frequency : 124.999MHz

Operating Temperature : -40℃~+85℃

Description : ±20ppm 3.3V 124.999MHz SMD7050-6P Programmable Oscillators RoHS

Mfr. Part # : 511NCB-AAAG

Model Number : 511NCB-AAAG

Package : SMD7050-6P

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Product Overview

The Si510/511 XO from Skyworks Solutions utilizes advanced DSPLL technology to generate any frequency from 100 kHz to 250 MHz using a single fixed crystal. This IC-based approach offers enhanced reliability, improved mechanical robustness, and excellent stability, along with superior supply noise rejection for low jitter clock generation in noisy environments. The devices are factory-configurable for various user specifications, including frequency, supply voltage, output format, and stability, with short lead times and no NRE charges. Crystal ESR and DLD are individually production-tested for guaranteed performance and reliability.

Product Attributes

  • Brand: Skyworks Solutions
  • Technology: DSPLL
  • Compliance: Pb-free, RoHS compliant

Technical Specifications

ParameterSymbolTest ConditionMinTypMaxUnit
Operating Specifications (VDD = 1.8 V 5%, 2.5 or 3.3 V 10%, TA = 40 to +85 oC)
Supply VoltageVDD3.3 V option2.973.33.63V
2.5 V option2.252.52.75V
1.8 V option1.711.81.89V
Supply CurrentIDDCMOS, 100 MHz, single-ended2126mA
LVDS (output enabled)1923mA
LVPECL (output enabled)3943mA
HCSL (output enabled)4144mA
Tristate (output disabled)18mA
OE "1" SettingVIHSee Note0.80 x VDDV
OE "0" SettingVILSee Note0.20 x VDDV
OE Internal Pull-Up/Pull-Down ResistorRI45k
Operating TemperatureTA4085oC
Output Clock Frequency Characteristics (VDD = 1.8 V 5%, 2.5 or 3.3 V 10%, TA = 40 to +85 oC)
Nominal FrequencyFOCMOS, Dual CMOS0.1212.5MHz
LVDS/LVPECL/HCSL0.1250MHz
Total Stability (includes initial accuracy, temp, VDD change, load change, aging)Grade C30+30ppm
Grade B50+50ppm
Grade A100+100ppm
Temperature StabilityGrade C20+20ppm
Grade B25+25ppm
Grade A50+50ppm
Startup TimeTSUMinimum VDD until FO within spec10ms
Disable TimeTDFO 10 MHz5s
FO < 10 MHz40s
Enable TimeTEFO 10 MHz20s
FO < 10 MHz60s
Output Clock Levels and Symmetry (VDD = 1.8 V 5%, 2.5 or 3.3 V 10%, TA = 40 to +85 oC)
CMOS Output Logic HighVOH0.85 x VDDV
CMOS Output Logic LowVOL0.15 x VDDV
CMOS Output Rise/Fall Time (20 to 80% VDD)TR/TF0.1 to 212.5 MHz, CL = 15 pF0.450.81.2ns
0.1 to 212.5 MHz, CL = no load0.30.60.9ns
LVPECL Output Rise/Fall Time (20 to 80% VDD)TR/TF100565ps
HCSL Output Rise/Fall Time (20 to 80% VDD)TR/TF100470ps
LVDS Output Rise/Fall Time (20 to 80% VDD)TR/TF350800ps
LVPECL Output Common ModeVOC50 to VDD 2 V, single-endedVDD 1.4 VV
LVPECL Output SwingVO50 to VDD 2 V, single-ended0.550.80.90VPPSE
LVDS Output Common ModeVOC100 line-line, VDD = 3.3/2.5 V1.131.231.33V
100 line-line, VDD = 1.8 V0.830.921.00V
LVDS Output SwingVOSingle-ended, 100 differential termination0.250.350.45VPPSE
HCSL Output Common ModeVOC50 to ground0.350.380.42V
HCSL Output SwingVOSingle-ended0.580.730.85VPPSE
Duty CycleDCAll formats485052%
Output Clock Jitter and Phase Noise (LVPECL) (VDD = 2.5 or 3.3 V 10%, TA = 40 to +85 oC; Output Format = LVPECL)
Period Jitter (RMS)JPRMS10k samples1.3ps
Period Jitter (Pk-Pk)JPPKPK10k samples11ps
Phase Jitter (RMS)J1.875 MHz to 20 MHz integration bandwidth (brickwall)0.310.5ps
12 kHz to 20 MHz integration bandwidth (brickwall)0.81.0ps
Phase Noise, 156.25 MHzN100 Hz86dBc/Hz
1 kHz109dBc/Hz
10 kHz116dBc/Hz
100 kHz123dBc/Hz
1 MHz136dBc/Hz
Additive RMS Jitter Due to External Power Supply NoiseJPSR10 kHz sinusoidal noise3.0ps
100 kHz sinusoidal noiseps

2411041604_SKYWORKS-511NCB-AAAG_C7187256.pdf


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