| Operating Specifications |
| Supply Voltage (3.3 V option) | VDD | | 2.97 | 3.3 | 3.63 | V |
| Supply Voltage (2.5 V option) | VDD | | 2.25 | 2.5 | 2.75 | V |
| Supply Voltage (1.8 V option) | VDD | | 1.71 | 1.8 | 1.89 | V |
| Supply Current (CMOS, 100 MHz, single-ended) | IDD | | | 21 | 26 | mA |
| Supply Current (LVDS, output enabled) | IDD | | | 19 | 23 | mA |
| Supply Current (LVPECL, output enabled) | IDD | | | 39 | 43 | mA |
| Supply Current (HCSL, output enabled) | IDD | | | 41 | 44 | mA |
| Supply Current (Tristate, output disabled) | IDD | | | | 18 | mA |
| Operating Temperature | TA | | 40 | | 85 | oC |
| Output Clock Frequency Characteristics |
| Nominal Frequency (CMOS, Dual CMOS) | FO | | 0.1 | | 212.5 | MHz |
| Nominal Frequency (LVDS/LVPECL/HCSL) | FO | | 0.1 | | 250 | MHz |
| Total Stability (Grade C) | | | 30 | | +30 | ppm |
| Total Stability (Grade B) | | | 50 | | +50 | ppm |
| Total Stability (Grade A) | | | 100 | | +100 | ppm |
| Temperature Stability (Grade C) | | | 20 | | +20 | ppm |
| Temperature Stability (Grade B) | | | 25 | | +25 | ppm |
| Temperature Stability (Grade A) | | | 50 | | +50 | ppm |
| Startup Time | TSU | Minimum VDD until output frequency (FO) within specification | | | 10 | ms |
| Disable Time (FO 10 MHz) | TD | | | | 5 | s |
| Disable Time (FO < 10 MHz) | TD | | | | 40 | s |
| Enable Time (FO 10 MHz) | TE | | | | 20 | s |
| Enable Time (FO < 10 MHz) | TE | | | | 60 | s |
| Output Clock Levels and Symmetry |
| CMOS Output Logic High | VOH | | 0.85 x VDD | | | V |
| CMOS Output Logic Low | VOL | | | | 0.15 x VDD | V |
| CMOS Output Rise/Fall Time (20 to 80% VDD, CL = 15 pF) | TR/TF | 0.1 to 212.5 MHz | 0.45 | 0.8 | 1.2 | ns |
| CMOS Output Rise/Fall Time (20 to 80% VDD, CL = no load) | TR/TF | 0.1 to 212.5 MHz | 0.3 | 0.6 | 0.9 | ns |
| LVPECL Output Rise/Fall Time (20 to 80% VDD) | TR/TF | | 100 | | 565 | ps |
| HCSL Output Rise/Fall Time (20 to 80% VDD) | TR/TF | | 100 | | 470 | ps |
| LVDS Output Rise/Fall Time (20 to 80% VDD) | TR/TF | | 350 | | 800 | ps |
| Duty Cycle | DC | All formats | 48 | 50 | 52 | % |
| Output Clock Jitter and Phase Noise (LVPECL) |
| Period Jitter (RMS) | JPRMS | 10k samples | | | 1.3 | ps |
| Period Jitter (Pk-Pk) | JPPKPK | 10k samples | | | 11 | ps |
| Phase Jitter (RMS) (1.875 MHz to 20 MHz integration bandwidth) | J | | | 0.31 | 0.5 | ps |
| Phase Jitter (RMS) (12 kHz to 20 MHz integration bandwidth) | J | | | 0.8 | 1.0 | ps |
