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crystal oscillator SKYWORKS 511JBA-BBAG with wide frequency range and configurable user specifications

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crystal oscillator SKYWORKS 511JBA-BBAG with wide frequency range and configurable user specifications

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Frequency Stability : ±25ppm

Output Type : LVDS

Voltage - Supply : 1.8V

Frequency : 169.999MHz

Description : ±25ppm LVDS 1.8V 169.999MHz SMD5032-6P Programmable Oscillators RoHS

Mfr. Part # : 511JBA-BBAG

Model Number : 511JBA-BBAG

Package : SMD5032-6P

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Skyworks Si510/511 Crystal Oscillator (XO)

The Si510/511 XO utilizes Skyworks Solutions' advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike traditional XOs requiring a different crystal for each output frequency, this solution uses one fixed crystal and a proprietary DSPLL synthesizer. This IC-based approach enhances reliability, mechanical robustness, and stability. It also offers superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested for guaranteed performance and reliability. The Si510/511 is factory-configurable for various user specifications, including frequency, supply voltage, output format, output enable polarity, and stability, eliminating long lead times and NRE charges.

Product Attributes

  • Brand: Skyworks Solutions, Inc.
  • Technology: DSPLL
  • Certifications: Pb-free, RoHS compliant

Technical Specifications

ParameterSymbolTest ConditionMinTypMaxUnit
Operating Specifications
Supply VoltageVDD3.3 V option2.973.33.63V
2.5 V option2.252.52.75V
1.8 V option1.711.81.89V
Supply CurrentIDDCMOS, 100 MHz, single-ended2126mA
LVDS (output enabled)1923mA
LVPECL (output enabled)3943mA
HCSL (output enabled)4144mA
Tristate (output disabled)18mA
Operating TemperatureTA4085oC
Output Clock Frequency Characteristics
Nominal FrequencyFOCMOS, Dual CMOS0.1212.5MHz
LVDS/LVPECL/HCSL0.1250MHz
Total StabilityFrequency Stability Grade C30+30ppm
Frequency Stability Grade B50+50ppm
Frequency Stability Grade A100+100ppm
Startup TimeTSUMinimum VDD until output frequency (FO) within specification10ms
Disable TimeTDFO 10 MHz5s
FO < 10 MHz40s
Enable TimeTEFO 10 MHz20s
FO < 10 MHz60s
Output Clock Levels and Symmetry
CMOS Output Logic HighVOH0.85 x VDDV
CMOS Output Logic LowVOL0.15 x VDDV
CMOS Output Rise/Fall Time (20 to 80% VDD)TR/TF0.1 to 212.5 MHz, CL = 15 pF0.450.81.2ns
LVPECL Output Rise/Fall Time (20 to 80% VDD)TR/TF100565ps
HCSL Output Rise/Fall Time (20 to 80% VDD)TR/TF100470ps
LVDS Output Rise/Fall Time (20 to 80% VDD)TR/TF350800ps
Duty CycleDCAll formats485052%
Output Clock Jitter and Phase Noise (LVPECL)
Period Jitter (RMS)JPRMS10k samples1.3ps
Period Jitter (Pk-Pk)JPPKPK10k samples11ps
Phase Jitter (RMS)J1.875 MHz to 20 MHz integration bandwidth (brickwall)0.310.5ps
12 kHz to 20 MHz integration bandwidth (brickwall)0.81.0ps
Additive RMS Jitter Due to External Power Supply NoiseJPSR10 kHz sinusoidal noise3.0ps

2411041604_SKYWORKS-511JBA-BBAG_C7024341.pdf


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