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MEMS based CMOS oscillator MICROCHIP DSC1001DI5-100.0000 with wide frequency range and jitter stability

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MEMS based CMOS oscillator MICROCHIP DSC1001DI5-100.0000 with wide frequency range and jitter stability

Voltage - Supply : 1.8V~3.3V

Frequency Stability : ±10ppm

Description : 1.8V~3.3V SMD2520-4P Oscillators RoHS

Mfr. Part # : DSC1001DI5-100.0000

Model Number : DSC1001DI5-100.0000

Package : SMD2520-4P

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Product Overview

The DSC1001/3/4 is a silicon MEMS-based CMOS oscillator family offering excellent jitter and stability over a wide range of supply voltages and temperatures. Its crystal-less design provides high reliability, making it suitable for rugged, industrial, and portable applications. Available in industry-standard packages, it serves as a pin-for-pin replacement for standard crystal oscillators.

Product Attributes

Brand: Microchip Technology Inc.
Material: Silicon MEMS
Certifications: Pb Free, RoHS, Reach SVHC Compliant, AEC-Q100 Reliability Qualified

Technical Specifications

Parameter	Symbol	Min.	Typ.	Max.	Units	Conditions
General
Frequency Range	F0	1		150	MHz	Single Frequency
Frequency Tolerance	Δf			±10	ppm	Includes frequency variations due to initial tolerance, temperature and power supply voltage
Frequency Tolerance	Δf			±20	ppm
Frequency Tolerance	Δf			±25	ppm
Frequency Tolerance	Δf			±50	ppm
Aging	Δf			±5	ppm	1 year @ +25°C
Standby Supply Current	IDD			15	µA	T = +25°C
Output Startup Time	tSU		1.0	1.3	ms	T = +25°C (Note 1)
Output Disable Time	tDA		20	100	ns
Output Duty Cycle	SYM	45		55	%
Input Logic Level High	VIH	0.75 x VDD			V
Input Logic Level Low	VIL			0.25 x VDD	V	VDD = 1.8V
Supply Current, No Load	IDD		6.0	6.3	mA	1 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		6.5	7.1	mA	27 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		7.2	8.5	mA	70 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		8.3	11.9	mA	150 MHz, CL = 0 pF, RL = ∞, T = +25°C
Output Logic Level High	VOH	0.8 x VDD			V	6 mA, DSC1004, CL = 40 pF
Output Logic Level High	VOH	0.8 x VDD			V	6 mA, DSC1003, CL = 25 pF
Output Logic Level High	VOH	0.8 x VDD			V	4 mA, DSC1001, CL = 15 pF
Output Logic Level Low	VOL			0.2 x VDD	V	6 mA, DSC1004, CL = 40 pF
Output Logic Level Low	VOL			0.2 x VDD	V	6 mA, DSC1003, CL = 25 pF
Output Logic Level Low	VOL			0.2 x VDD	V	4 mA, DSC1001, CL = 15 pF
Output Transition Rise Time	tR		1.4	3.0	ns	DSC1001, CL = 15 pF, T = +25°C, 20% to 80%
Output Transition Rise Time	tR		1.5	3.0	ns	DSC1003, CL = 25 pF, T = +25°C, 20% to 80%
Output Transition Rise Time	tR		1.8	3.0	ns	DSC1004, C2 = 40 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		1.0	3.0	ns	DSC1001, CL = 15 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		1.1	3.0	ns	DSC1003, CL = 25 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		1.2	3.0	ns	DSC1004, C2 = 40 pF, T = +25°C, 20% to 80%
Jitter, Max. Cycle-to-Cycle	JCC		60		ps	f = 100 MHz (Note 2)
Period Jitter	JP		10	15	psRMS	f = 100 MHz (Note 2)
VDD = 2.5V (TA = +85°C unless otherwise specified)
Supply Current, No Load	IDD		6.0	6.4	mA	1 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		6.7	7.5	mA	27 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		7.7	9.4	mA	70 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		9.6	13.9	mA	150 MHz, CL = 0 pF, RL = ∞, T = +25°C
Output Logic Level High	VOH	0.9 x VDD			V	6 mA, DSC1004, CL = 40 pF
Output Logic Level High	VOH	0.8 x VDD			V	6 mA, DSC1003, CL = 25 pF
Output Logic Level High	VOH	0.8 x VDD			V	4 mA, DSC1001, CL = 15 pF
Output Logic Level Low	VOL			0.1 x VDD	V	6 mA, DSC1004, CL = 40 pF
Output Logic Level Low	VOL			0.2 x VDD	V	6 mA, DSC1003, CL = 25 pF
Output Logic Level Low	VOL			0.2 x VDD	V	4 mA, DSC1001, CL = 15 pF
Output Transition Rise Time	tR		1.0	2.0	ns	DSC1001, CL = 15 pF, T = +25°C, 20% to 80%
Output Transition Rise Time	tR		1.1	2.0	ns	DSC1003, CL = 25 pF, T = +25°C, 20% to 80%
Output Transition Rise Time	tR		1.2	2.0	ns	DSC1004, C2 = 40 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		0.9	2.0	ns	DSC1001, CL = 15 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		1.0	2.0	ns	DSC1003, CL = 25 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		1.1	2.0	ns	DSC1004, C2 = 40 pF, T = +25°C, 20% to 80%
Jitter, Max. Cycle-to-Cycle	JCC		50		ps	f = 100 MHz (Note 2)
Period Jitter	JP		5	10	psRMS	f = 100 MHz (Note 2)
VDD = 3.3V (TA = +85°C unless otherwise specified)
Supply Current, No Load	IDD		6.0	6.5	mA	1 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		6.8	8.0	mA	27 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		8.2	10.5	mA	70 MHz, CL = 0 pF, RL = ∞, T = +25°C
Supply Current, No Load	IDD		10.8	16.6	mA	150 MHz, CL = 0 pF, RL = ∞, T = +25°C
Output Logic Level High	VOH	0.9 x VDD			V	8 mA, DSC1004, CL = 40 pF
Output Logic Level High	VOH	0.9 x VDD			V	6 mA, DSC1003, CL = 25 pF
Output Logic Level High	VOH	0.8 x VDD			V	4 mA, DSC1001, CL = 15 pF
Output Logic Level Low	VOL			0.1 x VDD	V	8 mA, DSC1004, CL = 40 pF
Output Logic Level Low	VOL			0.1 x VDD	V	6 mA, DSC1003, CL = 25 pF
Output Logic Level Low	VOL			0.2 x VDD	V	4 mA, DSC1001, CL = 15 pF
Output Transition Rise Time	tR		1.0	2.0	ns	DSC1001, CL = 15 pF, T = +25°C, 20% to 80%
Output Transition Rise Time	tR		1.1	2.0	ns	DSC1003, CL = 25 pF, T = +25°C, 20% to 80%
Output Transition Rise Time	tR		1.2	2.0	ns	DSC1004, C2 = 40 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		0.9	2.0	ns	DSC1001, CL = 15 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		1.0	2.0	ns	DSC1003, CL = 25 pF, T = +25°C, 20% to 80%
Output Transition Fall Time	tF		1.1	2.0	ns	DSC1004, C2 = 40 pF, T = +25°C, 20% to 80%
Jitter, Max. Cycle-to-Cycle	JCC		50		ps	f = 100 MHz (Note 2)
Period Jitter	JP		5	10	psRMS	f = 100 MHz (Note 2)
Temperature Specifications
Operating Temperature Range	TA	–40		+105	°C
Operating Temperature Range	TA	–40		+85	°C	Ordering Option L
Operating Temperature Range	TA	–20		+70	°C	Ordering Option I
Junction Operating Temperature	TJ			+150	°C
Storage Temperature Range	TA	–55		+150	°C
Soldering Temperature Range	TS			+260	°C	40 sec. max

2411041600_MICROCHIP-DSC1001DI5-100-0000_C1671172.pdf

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