| Frequency Range |
| Output Frequency Range | f | 1 | - | 110 | MHz | - |
| Frequency Stability and Aging |
| Frequency Stability | F_stab | -20 | - | +20 | ppm | Inclusive of initial tolerance at 25C, 1st year aging at 25C, and variations over operating temperature, rated power supply voltage and load. |
| | -25 | - | +25 | ppm | - |
| | -50 | - | +50 | ppm | - |
| Operating Temperature Range |
| Operating Temperature Range | T_use | -20 | - | +70 | C | Commercial |
| | -40 | - | +85 | C | Industrial |
| Supply Voltage and Current Consumption |
| Supply Voltage | Vdd | 2.25 | 2.5 | 2.75 | V | - |
| | 2.52 | 2.8 | 3.08 | V | - |
| | 2.7 | 3.0 | 3.3 | V | - |
| | 2.97 | 3.3 | 3.63 | V | - |
| | 2.25 | - | 3.63 | V | - |
| Current Consumption | Idd | - | 3.8 | 4.5 | mA | No load condition, f = 20 MHz, Vdd = 2.8V to 3.3V |
| | - | 3.7 | 4.2 | mA | No load condition, f = 20 MHz, Vdd = 2.5V |
| | - | 3.5 | 4.1 | mA | No load condition, f = 20 MHz, Vdd = 1.8V |
| OE Disable Current | I_OD | - | - | 4.2 | mA | Vdd = 2.5V to 3.3V, OE = GND, Output in high-Z state |
| | - | - | 4.0 | mA | Vdd = 1.8V, OE = GND, Output in high-Z state |
| Standby Current | I_std | - | 2.1 | 4.3 | A | ST = GND, Vdd = 2.8V to 3.3V, Output is weakly pulled down |
| | - | 1.1 | 2.5 | A | ST = GND, Vdd = 2.5V, Output is weakly pulled down |
| | - | 0.2 | 1.3 | A | ST = GND, Vdd = 1.8V, Output is weakly pulled down |
| LVCMOS Output Characteristics |
| Duty Cycle | DC | 45 | - | 55 | % | All Vdds. See Duty Cycle definition in Figure 3 and Footnote 8 |
| Rise/Fall Time | Tr, Tf | - | 1 | 2 | ns | Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80% |
| | - | 1.3 | 2.5 | ns | Vdd =1.8V, 20% - 80% |
| | - | - | 2 | ns | Vdd = 2.25V - 3.63V, 20% - 80% |
| Output High Voltage | VOH | 90% | - | - | Vdd | IOH = -4 mA (Vdd = 3.0V or 3.3V); IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V); IOH = -2 mA (Vdd = 1.8V) |
| Output Low Voltage | VOL | - | - | 10% | Vdd | IOL = 4 mA (Vdd = 3.0V or 3.3V); IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V); IOL = 2 mA (Vdd = 1.8V) |
| Input Characteristics |
| Input High Voltage | VIH | 70% | - | - | Vdd | Pin 1, OE or ST |
| Input Low Voltage | VIL | - | - | 30% | Vdd | Pin 1, OE or ST |
| Input Pull-up Impedance | Z_in | 50 | 87 | 150 | k | Pin 1, OE logic high or logic low, or ST logic high |
| | 2 | - | - | M | Pin 1, ST logic low |
| Startup and Resume Timing |
| Startup Time | T_start | - | - | 5 | ms | Measured from the time Vdd reaches its rated minimum value |
| Enable/Disable Time | T_oe | - | - | 130 | ns | f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles |
| Resume Time | T_resume | - | - | 5 | ms | Measured from the time ST pin crosses 50% threshold |
| Jitter |
| RMS Period Jitter | T_jitt | - | 1.8 | 3 | ps | f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V |
| | - | 1.8 | 3 | ps | f = 75 MHz, Vdd = 1.8V |
| Peak-to-peak Period Jitter | T_pk | - | 12 | 25 | ps | f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V |
| | - | 14 | 30 | ps | f = 75 MHz, Vdd = 1.8V |
| RMS Phase Jitter (random) | T_phj | - | 0.5 | 0.9 | ps | f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz |
| | - | 1.3 | 2 | ps | f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz |
