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Crystal Oscillator Silicon Labs 510BBA100M000BAG Featuring DSPLL Technology for Accurate Frequency

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Crystal Oscillator Silicon Labs 510BBA100M000BAG Featuring DSPLL Technology for Accurate Frequency

Description : SMD5032-6P Oscillators RoHS

Mfr. Part # : 510BBA100M000BAG

Model Number : 510BBA100M000BAG

Package : SMD5032-6P

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Product Overview

The Si510/511 Crystal Oscillator (XO) from Silicon Laboratories utilizes advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz using a single fixed crystal. This IC-based approach enhances reliability, mechanical robustness, and stability while offering superior supply noise rejection for low jitter clock generation in noisy environments. The device is factory-configurable for various user specifications, including frequency, supply voltage, output format, and stability, with short lead times and no NRE charges.

Product Attributes

Brand: Silicon Laboratories
Technology: DSPLL
Certifications: Pb-free, RoHS compliant
Packaging: 5 x 7 mm, 3.2 x 5 mm, and 2.5 x 3.2 mm
Operation Temperature: 40 to 85 C

Technical Specifications

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit	Notes
Operating Specifications
Supply Voltage	VDD	3.3 V option	2.97	3.3	3.63	V
		2.5 V option	2.25	2.5	2.75	V
		1.8 V option	1.71	1.8	1.89	V
Supply Current	IDD	CMOS, 100 MHz, single-ended		21	26	mA
		LVDS (output enabled)		19	23	mA
		LVPECL (output enabled)		39	43	mA
		HCSL (output enabled)		41	44	mA
		Tristate (output disabled)			18	mA
OE Setting	VIH	OE "1"	0.80 x VDD			V	Active high and active low polarity OE options available. Active high option includes an internal pull-up. Active low option includes an internal pull-down.
	VIL	OE "0"			0.20 x VDD	V
OE Internal Resistor	RI			45		k
Operating Temperature	TA		40		85	C
Output Clock Frequency Characteristics
Nominal Frequency	FO	CMOS, Dual CMOS	0.1		212.5	MHz
	FO	LVDS/LVPECL/HCSL	0.1		250	MHz
Total Stability		Grade C	30		+30	ppm	Includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration (not under operation), and 10 years aging at 40 C.
		Grade B	50		+50	ppm
		Grade A	100		+100	ppm
Temperature Stability		Grade C	20		+20	ppm
		Grade B	25		+25	ppm
		Grade A	50		+50	ppm
Startup Time	TSU	Minimum VDD until output frequency (FO) within specification			10	ms
Disable Time	TD	FO 10 MHz			5	s
		FO < 10 MHz			40	s
Enable Time	TE	FO 10 MHz			20	s
		FO < 10 MHz			60	s
Output Clock Levels and Symmetry
CMOS Output Logic High	VOH		0.85 x VDD			V
CMOS Output Logic Low	VOL				0.15 x VDD	V
CMOS Output Rise/Fall Time	TR/TF	0.1 to 212.5 MHz, CL = 15 pF	0.45	0.8	1.2	ns
		0.1 to 212.5 MHz, CL = no load	0.3	0.6	0.9	ns
LVPECL Output Rise/Fall Time	TR/TF		100		565	ps
HCSL Output Rise/Fall Time	TR/TF		100		470	ps
LVDS Output Rise/Fall Time	TR/TF		350		800	ps
LVPECL Output Common Mode	VOC	50 to VDD 2 V, single-ended		VDD 1.4 V		V
LVPECL Output Swing	VO	50 to VDD 2 V, single-ended	0.55	0.8	0.90	VPPSE
LVDS Output Common Mode	VOC	100 line-line, VDD = 3.3/2.5 V	1.13	1.23	1.33	V
		100 line-line, VDD = 1.8 V	0.83	0.92	1.00	V
LVDS Output Swing	VO	Single-ended, 100 differential termination	0.25	0.35	0.45	VPPSE
HCSL Output Common Mode	VOC	50 to ground	0.35	0.38	0.42	V
HCSL Output Swing	VO	Single-ended	0.58	0.73	0.85	VPPSE
Duty Cycle	DC	All formats	48	50	52	%
Output Clock Jitter and Phase Noise (LVPECL)
Period Jitter (RMS)	JPRMS	10k samples			1.3	ps	Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz.
Period Jitter (Pk-Pk)	JPPKPK	10k samples			11	ps
Phase Jitter (RMS)	J	1.875 MHz to 20 MHz integration bandwidth (brickwall)		0.31	0.5	ps	Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
		12 kHz to 20 MHz integration bandwidth (brickwall)		0.8	1.0	ps
Phase Noise, 156.25 MHz	N	100 Hz		86		dBc/Hz
		1 kHz		109		dBc/Hz
		10 kHz		116		dBc/Hz
		100 kHz		123		dBc/Hz
		1 MHz		136		dBc/Hz
Additive RMS Jitter Due to External Power Supply Noise	JPSR	10 kHz sinusoidal noise		3.0		ps	156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
		100 kHz sinusoidal noise		3.5		ps
		500 kHz sinusoidal noise		3.5		ps
		1 MHz sinusoidal noise		3.5		ps
Spurious	SPR	LVPECL output, 156.25 MHz, offset>10 kHz		75		dBc
Output Clock Jitter and Phase Noise (LVDS)
Period Jitter (RMS)	JPRMS	10k samples			2.1	ps	Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz.
Period Jitter (Pk-Pk)	JPPKPK	10k samples			18	ps
Phase Jitter (RMS)	J	1.875 MHz to 20 MHz integration bandwidth (brickwall)		0.25	0.55	ps	Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
		12 kHz to 20 MHz integration bandwidth (brickwall)		0.8	1.0	ps
Phase Noise, 156.25 MHz	N	100 Hz		86		dBc/Hz
		1 kHz		109		dBc/Hz
		10 kHz		116		dBc/Hz
		100 kHz		123		dBc/Hz
		1 MHz		136		dBc/Hz
Spurious	SPR	LVPECL output, 156.25 MHz, offset>10 kHz		75		dBc

2410121928_SILICON-LABS-510BBA100M000BAG_C1671193.pdf

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